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IT8710F low pin count input / output (lpc i/o) preliminary programming guide v0.1
notice: the information provided in this publication is believed to be accurate. integrated circuit s sold by ite are covered by the warranty and patent indemnification provisions stipulated in the terms ite terms and conditions of sale, as revised from time to time. ite makes no warranty, expressed, statutory, implied, or by description, regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement, except as specifically provided in the ite terms and conditions of sale. furthermore, ite makes no warranty of merchantability or fitness for any pu rpose. ite reserves the right to halt production or modify specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the specification and other information included in this publication is current before pl acing product orders. products described herein are intended for use in normal commercial applications. applications involving unusual environment or reliability requirements (e.g., military equipment or medical life - support equipment) are specifically not recommended without additional processing by ite for such applications. all trademarks are the sole property of their respective owners. to find out more about ite, visit our world wide web site at: http://www.it e.com.tw http://www.iteusa.com copyright ? ite, inc. 2001 the terms and conditions in the back of this documentation govern all sales by ite. ite will not be bound by any terms inconsistent with these unless ite agrees otherwise in writing. acceptance of buyer?s order shall be based on these terms.
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com i contents contents 1. overview ................................ ................................ ................................ ................................ ............................... 1 2. block diagram ................................ ................................ ................................ ................................ ...................... 3 3. pin configuration ................................ ................................ ................................ ................................ .................. 5 4. programming sequence and flow charts ................................ ................................ ................................ ......... 7 4.1 configuring sequence description ................................ ................................ ................................ .......... 7 4.2 fdc (ldn=00h) ................................ ................................ ................................ ................................ ........ 8 4.3 serial port 1 (ldn=01h) ................................ ................................ ................................ ........................... 9 4.4 serial port 2 (ldn=02h) ................................ ................................ ................................ ......................... 10 4.4.1 serial port 2 configuration registers (ldn=02h) ................................ ................................ . 10 4.4.1.1 serial port 2 base address msb register (index=60h, default=02h) ....................... 10 4.4.1.2 serial port 2 base address lsb register (index=61h, default=f8h) ........................ 10 4.4.1.3 serial port 2 interrupt level select (index=70h, default=03h) ................................ . 10 4.4.1.4 serial port 2 special configuration register 1 (index=f0h, default=00h) ............... 11 4.4.1.5 serial port 2 special configuration register 2 (index=f1h, default=50h) ............... 11 4.4.1.6 serial port 2 special configuration register 3 (index=f2h, default=0 0h) ............... 11 4.4.1.7 serial port 2 special configuration register 4 (index=f3h, default=7fh) .............. 12 4.5 parallel port (ldn=03h) ................................ ................................ ................................ ......................... 14 4.5.1 spp and epp modes ................................ ................................ ................................ .............. 14 4.6 swc (ldn=04h) ................................ ................................ ................................ ................................ ..... 17 4.7 game port (ldn=08) ................................ ................................ ................................ .............................. 17 4.7.1 game port (base+0h) ................................ ................................ ................................ ............. 20 4.8 cir (ldn=09) ................................ ................................ ................................ ................................ ......... 20 4.9 midi (ld n=0ah) ................................ ................................ ................................ ................................ ..... 23 figures figure 4 - 1. enter the mb pnp mode flow chart ................................ ................................ ................................ ..... 7 figure 4 - 2. fdc control flow chart ................................ ................................ ................................ ......................... 8 figure 4 - 3. serial port control flow chart ................................ ................................ ................................ ............... 9 figure 4 - 4. smart card operating sequence example ................................ ................................ ........................ 12 figure 4 - 5. flow chart for it8710 smart card reader ................................ ................................ ......................... 13 figure 4 - 6. select parallel port modes flow chart ................................ ................................ ............................... 16 figure 4 - 7. game port registers ................................ ................................ ................................ ............................ 18 figure 4 - 8. game port i/o flow chart ................................ ................................ ................................ ................... 19 figure 4 - 9. cir rx flow chart ................................ ................................ ................................ ............................... 21 figure 4 - 10. cir tx flow chart ................................ ................................ ................................ ............................. 22 figure 4 - 11. midi i/o flow chart ................................ ................................ ................................ ............................ 24
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com ii IT8710F programming guide tables table 4 - 1. fdc configuration registers ................................ ................................ ................................ .................. 8 table 4 - 2. serial port 1 configuration registers ................................ ................................ ................................ ..... 9 t able 4 - 3. serial port 2 configuration registers ................................ ................................ ................................ ... 10 table 4 - 4. parallel port configuration registers ................................ ................................ ................................ ... 14 table 4 - 5. address map an d bit map for spp and epp modes ................................ ................................ .......... 14 table 4 - 6. bit map of the ecp registers ................................ ................................ ................................ ............... 15 table 4 - 7. ecp register definitions ................................ ................................ ................................ ....................... 15 table 4 - 8. ecp mode descriptions ................................ ................................ ................................ ........................ 15 table 4 - 9. swc configuration registers ................................ ................................ ................................ ............... 17 table 4 - 10. game port configuration registers ................................ ................................ ................................ ... 17 table 4 - 11. consumer ir configuration registers ................................ ................................ ............................... 20 table 4 - 12. midi port con figuration registers ................................ ................................ ................................ ...... 23
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com dec. 27, 2001 specifications subject to change without notice 1 overview 1. overview the IT8710F is a lpc interface based highly integrated super i/o. the IT8710F provides the most commonly used legacy super i/o functionality. the device?s lpc interface complies with inte l ?lpc interface specification rev. 1.01?. the IT8710F meets the ?microsoft a pc98/pc99/pc2001 system design guide? requirements and is acpi compliant. features include one high - performance 2.88mb floppy disk controller, with digital data separator, suppo rting one 360k/720k/1.2m/1.44m/2.88m floppy disk drive. one multi - mode high - performance parallel port features the bi - directional standard parallel port (spp), the enhanced parallel port (epp v. 1.7 and epp v. 1.9 are supported), and the ieee 1284 complian t extended capabilities port (ecp). two 16c550 standard compatible enhanced uarts perform asynchronous communication, and support sir. the smart card interface is internally connected to uart2. consumer ir, midi and game port are also supported. there is a lso a flash rom interface with address (fa[0:18]), data (fd[0:7]), supporting three control signals fcs#, fwe# and frd#. these 9 logical devices can be individually enabled or disabled via software configuration registers. the IT8710F utilizes power - effi cient circuitry to reduce power consumption. once a logical device is disabled, the inputs are gated inhibit, the outputs are tri - state and the input clock is disabled. the IT8710F requires a single 24/48 mhz clock input and operates with a single +3.3v po wer supply. the IT8710F is available in 100 - pin pqfp (plastic quad flat package).
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 2
www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 3 block diagram 2. block diagram lpc interface central interface bus 16c550 uart2 or scr ieee1284 parallel port flash rom i/f controller flash rom interface parallel port interface clock gen. 24/48 mhz clock lpc bus 16c550 uart1 serial port 1 interface game game interface floppy disk controller floppy drive interface serial port 2 or scr or sir general purpose i/o i/o ports pci pme# midi midi consumer ir consumer ir interface
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www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 5 pin configuration 3. pin configuration IT8710F 100-pqfp cirtx/fa16/gp40* fa15/gp37 vcch fa14/gp36* fa13/gp35* fa12/vid4/gp34 fa11/vid3/gp33 fa10/vid2/gp32 fa9/vid1/gp31 fa8/vid0/gp30 fa7/gp27 fa6/gp26 fa5/gp25 fa4/gp24 fa3/gp23 fa2/gp22 fa1/gp21 fa0/gp20 fd7/gp17 fd6/gp16 fd5/sout2/gp15 fd4/dsr2#/gp14 fd3/rts2#/gp13 fd2/dtr2#/gp12 fd1/cts2#/gp11 fd0/ri2#/gp10 gnd fcs#/sin2/gp63 frd#/dcd2#/gp62 cirrx/gp41* irtx/fa17/gp42* irrx/gp43* pme# scpsnt#/gp44 scrst/gp45 scpwr/gp46 scclk/gp47 scio/gp60 ldrq# lframe# lreset# serirq lad0 lad1 lad2 lad3 pciclk densel# mtra# drva# clkin gnd vcc wdata# step# hdsel# wgate# dir# rdata# dskchg# trk0# index# wpt# pe slct ack# busy slin# init# err# afd# stb# pd0 pd1 pd2 pd3 gnd pd4 pd5 fwe#/jvr/gp61 jacx/gp50 jacy/gp51 jbcx/gp52 jbcy/gp53 jab1/gp54 jab2/gp55 jbb1/gp56 jbb2/gp57 vcc dsr1# sout1/fa18/jp3 sin1 rts1#/jp2 dtr1#/jp1 dcd1# ri1# cts1# pd7 pd6 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 gnd top view
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www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 7 programming sequence and flow charts 4. programming sequence and flow charts 4.1 configuring sequen ce description hardware reset wait for key string is the data "87h" ? mb pnp mode "87h"? y n any other i/o transition cycle i/o write to 2eh (or 4eh) y wait for next data any other i/o transition cycle i/o write to 2eh (or 4eh) n figure 4 - 1 . enter the mb pnp mode flow chart (1) enter the mb pnp mode to enter the mb pnp mode, 2 specific i/o write operations (87h) must be performed during th e ?wait for key? state. the addresses of the configuration index/data register pair are determined by the power - on strapping of pin 89 (jp3). 2eh/2fh is selected when the power - on strapping value of this pin is high (internal pull - up resistor); 4eh/4fh is selected when the power - on strapping value of this pin is low (external pull - down resistor). (2) modifying the data of the registers all configuration registers can be accessed after the mb pnp mode is accessed. before accessing a selected register, the content of index 07h must be changed to the ldn to which the register belongs, except some global registers. (3) exiting the mb pnp mode set bit 1 of the configure control register (index=02h) to ?1? to exit the mb pnp mode.
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 8 IT8710F programming guide 4.2 fdc (ldn=00h) table 4 - 1 . fdc configuration registers ldn index r/w default configuration register or action 00h 30h r/w 00h fdc activate 00h 60h r/w 03h fdc base address msb register 00h 61h r/w f0h fdc base address lsb register 00h 70h r/w 06h fdc interrupt level select 00h 74h r/w 02h fdc dma channel select 00h f0h r/w 00h fdc special configuration register 1 00h f1h r/w 00h fdc special configuration register 2 go in configuration out 2e87 out 2e87 read, write... set fdc command set ldn=00h out 2e 07 out 2f 00 get fdc base address out 2e 60 in 2 f out 2e 61 in 2 f figure 4 - 2 . fdc control flow chart
www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 9 programming sequence and flow charts 4.3 serial port 1 (ldn=01h) table 4 - 2 . serial port 1 configuration registers ldn index r/w default configuration register or action 01h 30h r/w 00h serial po rt 1 activate 01h 60h r/w 03h serial port 1 base address msb register 01h 61h r/w f8h serial port 1 base address lsb register 01h 70h r/w 04h serial port 1 interrupt level select 01h f0h r/w 00h serial port 1 special configuration register go in configuration out 2e 87 out 2e 87 read, write... set read or write command set ldn=01h out 2e 07 out 2f 01 get serial port 1 base address out 2e 60 in 2 f out 2e 61 in 2 f figure 4 - 3 . serial port control flow chart
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 10 IT8710F programming guide 4.4 serial port 2 (ldn=02h) table 4 - 3 . serial port 2 configuration registers ldn index r/w defa ult configuration register or action 02h 30h r/w 00h serial port 2 activate 02h 60h r/w 02h serial port 2 base address msb register 02h 61h r/w f8h serial port 2 base address lsb register 02h 70h r/w 03h serial port 2 interrupt level select 02h f0h r/ w 00h serial port 2 special configuration register 1 02h f1h r/w 50h serial port 2 special configuration register 2 02h f2h r/w 00h serial port 2 special configuration register 3 02h f3h r/w 7fh serial port 2 special configuration register 4 4.4.1 serial po rt 2 configuration registers (ldn=02h) 4.4.1.1 serial port 2 base address msb register (index=60h, default=02h) bit description 7 - 4 read only with ?0h? for base addresses [15:12]. 3 - 0 read/write , mapped as base addresses [11:8]. 4.4.1.2 serial port 2 base address ls b register (index=61h, default=f8h) bit description 7 - 3 read/write , mapped as base addresses [7:3]. 2 - 0 read only as ?000b.? 4.4.1.3 serial port 2 interrupt level select (index=70h, default=03h) bit description 7 - 4 reserved with default ?0h.? 3 - 0 select th e interrupt level note1 for serial port 2. note 1 : interrupt level mapping fh - dh: not valid ch: irq12 . . 3h: irq3 2h: not valid 1h: irq1 0h: no interrupt selected
www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 11 programming sequence and flow charts 4.4.1.4 serial port 2 special configuration register 1 (index=f0h, defaul t=00h) bit description 7 - 1 reserved 0 s2_irq_shr (serial port 2 interrupt request sharing) 0: normal (default). 1: enable s2 irq sharing. 4.4.1.5 serial port 2 special configuration register 2 (index=f1h, default=50h) bit description 7 ir_r2t_dly (ir rx t o tx delay mode) 0: transmission delays (40 bits) when the sir or askir is switched from rx mode to tx mode. (default) 1: no transmission delays (40 bits) when the sir or askir is switched from rx mode to tx mode. 6 ir_t2r_dly (ir tx to rx delay mode) 0: transmission delays (40 bits) when the sir or askir is switched from tx mode to rx mode. 1: no transmission delays (40 bits) when the sir or askir is switched from tx mode to rx mode (default). 5 reserved with default ?0b? 4 hf_dlx (half duplex enable) 0: full duplex 1: half duplex (default) 3 reserved with default ?0b? 2 - 0 s2_mod (serial port 2 mode) 000: standard (default) 001: irda sir 010: askir 100: smart card reader (scr) else: reserved 4.4.1.6 serial port 2 special configuration register 3 ( index=f2h, default=00h) bit description 7 com_pnp_en 0: disable com port device plug - and - play operation (default). 1: enable com port device plug - and - play operation. 6 - 5 reserved 4 pnp_id this bit is only available when bit 7=1. 0: pnp_id access mode (default). 1: normal plug - and - play operation mode. 3 reserved 2 scpwr_por (scpwr polarity) 0: active low (default). 1: active high. 1 - 0 scclk_sel1 - 0 (scclk frequency selection) 00: stop (default) 01: 3.5 mhz 10: 7.1 mhz 11: special frequency (96 mhz/sc div)
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 12 IT8710F programming guide 4.4.1.7 serial port 2 special configuration register 4 (index=f3h, default=7fh) bit description 7 reserved 6 - 0 scdiv6 - 0 (scclk special divisor). insert n power up, clock y atr reset card n1 decoding atr more protocols pts request pts confirm change protocol transfer protocol error idle clock stop n y y y h/w reset emergency remove waiting for icc insertion interrupt by uart sense present# power up fet to 5v, then allow clock out and reset control, i/o in receive mode active level may differ icc responses to answer-to-reset within 400 - 40000 clock cycles of scclk, if n1, then reset active high, if n2, then deactive power down finish y n remove n2 driver translates the atr if no protocol is available, then treat as all default setting; if more protocols are available, the driver can select a suitable transfer protocol ifd sends protocol-type-selection request, and intends to change xfer protocol if the icc accepts, then returns a confirm code both ifd and icc changed to new compromised protocol begin to xfer data for normal deactivation, the driver controls the ifd to enter deactive sequence stop clock then power down fet if users remove the icc at any time figure 4 - 4 . smart card opera ting sequence example
www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 13 programming sequence and flow charts go in i/o configuration out 2eh, 87h, 87h save original value set ldn=01h or 02h to select uart1 or uart2 configuration register bios level kernel mode driver uart function select: f1[2:0]=100b; smart card reader f2[1:0]=01b; scr_clksel = 3.5 mhz f2[1:0]=01b; scr_clksel = 3.5 mhz set baud rate = 9600 1. lcr[7] = 1b 2. dll[7:0] = 0ch 3. dlm[7:0] = 00h 4. lcr[7] = 0b enable fifo: write fcr[0] = 1b fcr[7:6] = 00b if fifo is enabled, read iir[7:6] = 11b out2 enable; reset scr and generate clock; 1. mcr [3] = 1b 2. mcr[1:0] = 00b 3. mcr[1:0] = 01b 4. mcr[1:0] = 11b wait for smart card atr and smart card command no parity; 8 data bits in width; 1 stop bit; lcr[3:0] = 0011b figure 4 - 5 . flow chart for it8710 smart card reader
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 14 IT8710F programming guide 4.5 parallel port (ldn=03h) table 4 - 4 . parallel port conf iguration registers ldn index r/w default configuration register or action 03h 30h r/w 00h parallel port activate 03h 60h r/w 03h parallel port primary base address msb register 03h 61h r/w 78h parallel port primary base address lsb register 03h 62h r/ w 07h parallel port secondary base address msb register 03h 63h r/w 78h parallel port secondary base address lsb register 03h 64h r/w 00h post data port base address msb register 03h 65h r/w 80h post data port base address lsb register 03h 70h r/w 07h parallel port interrupt level select 03h 74h r/w 03h parallel port dma channel select note1 03h f0h r/w 03h note2 parallel port special configuration register note 1: when the ecp mode is not enabled, this register is read only as ?04h?, and cannot be written. note 2: when the bit 2 of the primary base address lsb register of parallel port is set to 1, the epp mode cannot be enabled. bit 0 of this register is always 0. 4.5.1 spp and epp modes table 4 - 5 . addres s map and bit map for spp and epp modes register address r/w d0 d1 d2 d3 d4 d5 d6 d7 mode data port base 1+0h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 spp/epp status port base 1+1h ro tmout 1 1 err# slct pe ack# busy# spp/epp control port base 1+2h r/w stb a fd init slin irqe pddir 1 1 spp/epp epp address port base 1+3h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port0 base 1+4h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port1 base 1+5h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port2 base 1+6h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port3 base 1+7h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp note 1: the base address 1 depends on the logical device configuration registers of parallel port (0x60, 0x61).
www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 15 programming sequence and flow charts table 4 - 6 . bit map of the ecp registers register d7 d6 d5 d4 d3 d2 d1 d0 data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field dsr nbusy nack perror select nfault 1 1 1 dcr 1 1 pddir irqe selectin ninit autofd strobe cfifo parallel port data fifo ecpdfifo ecp data fifo tfifo test fifo cnfga 0 0 0 1 0 0 0 0 cnfgb 0 intrvalue 0 0 0 0 0 0 ecr mode nerrintren dmaen serviceintr full empty table 4 - 7 . ecp register definitions name address r/w ecp mode function data base 1 +000h r/w 000 - 001 data register ecpafifo base 1 +000h r/w 011 ecp fifo (address) dsr base 1 +001h r/w all status register dcr base 1 +002h r/w all control register cfifo base 2 +000h r/w 010 p arallel port data fifo ecpdfifo base 2 +000h r/w 011 ecp fifo (data) tfifo base 2 +000h r/w 110 test fifo cnfga base 2 +000h ro 111 configuration register a cnfgb base 2 +001h r/w 111 configuration register b ecr base 2 +002h r/w all extended control register table 4 - 8 . ecp mode descriptions mode description 000 standard parallel port mode 001 ps/2 parallel port mode 010 parallel port fifo mode 011 ecp parallel port mode 110 test mode 111 configur ation mode
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 16 IT8710F programming guide select spp, epp or ecp mode? go in configuration out 2e 87 out 2e 87 set ldn = 03h out 2e 07 out 2f 04 get parallel port base address out 2e 60 in 2 f out 2e 61 in 2 f select ecp mode out 2e f 0 out 2f 02 set dma 3 out 2e 74 out 2f 03 set spp mode out 2e f 0 out 2f 00 set epp mode out 2e f 0 out 2f 01 read, write... figure 4 - 6 . select parallel port modes flow chart
www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 17 programming sequence and flow charts 4.6 swc (ldn=04h) table 4 - 9 . swc configuration registers ldn index r/w power - well default configuration register or action 04h e0h r/w vsb -- swc status register 1 04h e1h r/w vsb -- swc status register 2 04h e2h r/w vsb 00h swc_sts1 to pme during vcc on enable register 04h e3h r/w vsb 00h swc_sts2 to pme duri ng vcc on enable register 04h e4h r/w vsb 00h swc_sts1 to pme during vcc off enable register 04h e5h r/w vsb 00h swc_sts1 to smi during vcc on enable register 04h e6h r/w vsb 00h swc_sts2 to smi during vcc on enable register 04h e7h r/w vsb 00h swc_ sts1 to smi during vcc off enable register 04h f0h r/w vsb 00h reserved register 04h f1h r/w vsb 00h reserved register 04h f2h r/w vsb 00h reserved register 04h f4h r/w vsb 00h reserved register 04h f5h r/w vsb - swc special code index register 04h f6h r/w vsb - swc special code data register 4.7 game port (ldn=08) table 4 - 10 . game port configuration registers ldn index r/w default configuration register or action 08h 30h r/w 00h game port activate 08 h 60h r/w 02h game port base address msb register 08h 61h r/w 01h game port base address lsb register
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 18 IT8710F programming guide game port registers b - # 2 b u t t o n b - # 1 b u t t o n a - # 2 b u t t o n b - # 1 b u t t o n b i t 7 b i t 6 b i t 5 b i t 4 b - y c o o r d i n a t e a - y c o o r d i n a t e b - x c o o r d i n a t e a - x c o o r d i n a t e b i t 3 b i t 2 b i t 1 b i t 0 r / w resistive input digital input figure 4 - 7 . game port registers
www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 19 programming sequence and flow charts go in configuration out 2e 87 out 2e 87 input, output set ldn = 08h out 2e 07 out 2f 08 get game port base address out 2e 60 in 2 f out 2e 61 in 2 f send game port message figure 4 - 8 . game port i/o flow chart the game port integrates four timers for two joysticks. the IT8710F allows the game port base address to be located within the host i/o address space 100h to 0fffh. currently, most game software assume that the game (or joystick) i/o port is located at 201h. a write to the game port base address will trigger four timers. a read from the same address returns four bits that correspond to the output from the four timers, and other four status bits corresponding to the joystick buttons will also be returned. a button value of 0 indicates that the button is pressed. when the game port base address is written, the x/y timer bits go high. once the game port base address is written, each tim er output remains high for a duration of time determined by the current joystick position.
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 20 IT8710F programming guide 4.7.1 game port (base+0h) bit signal description 7 jbb2 joystick b, button 2 (pin 56 of joystick connector) 6 jbb1 joystick b, button 1 (pin 55 of joystick connector ) 5 jbcy joystick b, coordinate y (pin 54 of joystick connector) 4 jbcx joystick b, coordinate x (pin 53 of joystick connector) 3 jab2 joystick a, button 2 (pin 52 of joystick connector) 2 jab1 joystick a, button 1 (pin 51 of joystick connector) 1 jac y joystick a, coordinate y (pin 50 of joystick connector) 0 jacx joystick a, coordinate x (pin 49 of joystick connector) 4.8 cir (ldn=09) table 4 - 11 . consumer ir configuration registers ldn index r/w default c onfiguration register or action 09h 30h r/w 00h consumer ir activate 09h 60h r/w 03h consumer ir base address msb register 09h 61h r/w 10h consumer ir base address lsb register 09h 70h r/w 0bh consumer ir interrupt level select 09h f0h r/w 00h consume r ir special configuration register a. set cir registers: tx: baud rate, frequency, pulse width, pulse mode, deferral mode, rle mode and fifo threshold. rx: baud rate frequency range, sync mode and fifo threshold. b. begin to transmit/receive data: tx: befor e transmitting any data, the tx fifo must be cleared first. the device then starts to transmit one frame data into the fifo. during data transmit, the tx fifo byte count must be monitored closely to ensure the byte count is remained below the maximum fifo value, for fifo to receive further data. it is recommended to clear the fifo data before the next frame data transmission can be started. rx: before transmitting any data, the rx fifo must be cleared first. rxen and rxend are then enabled, and rxact is a sserted low by writing 1 to clear this bit, as illustrated in the diagram on the next page.
www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 21 programming sequence and flow charts no go in i/o configuration save original value set ldn=09h enable cir, select interrupt level,clock select. hook system interrupt. set rx baud rate. set rx demodulation parameter: carrier range,sync mode. set rx fifo threshold. pio mode or interrupt mode? make sure rx fifo is cleared. set rcr register: rxen and rxend to 1. set rxact to 1 to assert low. wait data until timeout. interrupt mode pio mode identify if receiver data stored interrupt level is on isr. poll the rsr byte count register to monitor the received data. read data to main memory and decode. receive data over? go in i/o configuration. disable cir. restore parameter. yes figure 4 - 9 . cir rx flow chart
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 22 IT8710F programming guide set tx baud rate set tx modulation parameter: carrier frequency, pulse mode, pulse width, deferral mode. set tx fifo mode. make sure tx fifo byte count is 0. and txudr bit is 1. if fifo is not cleared again, then send data into fifo. identify if transmitter low data level interrupt is on isr. go in i/o configuration save original value pio mode or interrupt mode? poll thetsr register if byte count left is enough. data all sent out? send next data frame to fifo go in i/o configuration. disable cir. restore parameter. set ldn=09h enable cir, select interrupt level, clock select. hook system interrupt. interrupt mode pio mode yes figure 4 - 10 . cir tx flow chart
www.ite.com.tw IT8710F programming guide v0. 1 www.iteusa.com 23 programming sequence and flow charts 4.9 midi (ldn=0ah) table 4 - 12 . midi port configuration registers ldn index r/w default configuration register or action 0ah 30h r/w 00h midi port activate 0ah 60h r/w 03h midi port base address msb register 0ah 61h r/w 00h midi port base address lsb register 0ah 70h r/w 0ah midi port interrupt level select 0ah f0h r/w 00h midi port special configuration register the IT8710F supports the midi c apability by incorporating hardware to emulate the mpu - 401 in the uart mode. it is software compatible with mpu - 401 interface, but only supports the uart mode (non - intelligent mode). the uart is used to convert parallel data to the serial data required by midi. the serial data format is rs - 232 like: 1 start bit, 8 data bits, and 1 stop bit. the serial data rate is fixed at 31.25 kbaud. the mpu - 401 logical device occupies two consecutive i/o spaces. the device also uses an interrupt. both the base address an d the interrupt level are programmable. midi base+0 is the midi data port, and midi base+ 1 is the command/status port. midi data port: the midi data port is used to transmit and receive midi data. when in uart mode, all transmit data is transferred throu gh a 16 - byte fifo and receive data through another 16 - byte fifo. uart mode: 1. all reads of the data port, midi base+0, return the next byte in the receive buffer fifo. the serial data received from the midi_in pin is stored in the receive buffer fifo. the bit 7 rxs of the status register is updated to reflect the new receive buffer fifo status. the receive data available interrupt will be issued only if the fifo has reached its programmed trigger level. the interrupts will be cleared as soon as the fifo dro ps below its trigger level. the trigger level is programmable by changing bits 2 - 1 of the midi port special configuration register, ldn8_f0h. 2. all writes to the data port, midi base+0, are placed in the transmit buffer fifo. whenever the transmit buffer f ifo is not empty, the data bytes are read from the buffer in turn and sent out from the midi_out pin. the bit 6 txs of the status register is updated to reflect the new transmit buffer fifo status. 3. all writes to the command port, midi base+1, are monitore d and acknowledged below: ffh: set the interface into the initialization condition. the interface returns to the intelligent mode others: no operation
www.ite.com.tw IT8710F programming guide v0.1 www.iteusa.com 24 IT8710F programming guide go in configuration out 2e 87 out 2e 87 set ldn=0ah out 2e 07 out 2f 0a enable midi out 2e 30 out 2f 01 get midi base address out 2e 60 in 2 f out 2e 61 in 2 f set into uart mode out command/status port, 3 f h input, output send r/w command out data port, data or in data port, data figure 4 - 11 . mi di i/o flow chart
integrated technology express, inc. terms and conditions of sale (rev: may ?98) these terms and conditions of sale apply to all items designed, sold and/or made by integrated technology express, inc. (?ite taiwan?) and/or integrat ed technology express, inc. (?ite california?), and buyer agrees they apply to all such items. 0. parties ite taiwan is a company headquartered in the republic of china, taiwan, and incorporated under taiwan law, and ite california is a separate company in corporated under california law and headquartered in california. these two companies are independent, and, except as to the entity which invoices for goods delivered to it, buyer holds no rights against and has no commitments from ite california and/or it e taiwan. subject to the foregoing, ?seller? refers to the entity which invoices buyer for product, provided however that both ite taiwan and ite california shall each be entitled to claim protection under paragraphs 4(b) - 4(f), 5, 8, 9, 10, 11, 12 and 13 b elow. 1. acceptance of terms buyer accepts these terms (i) by written acceptance (by purchase order or otherwise), or (ii) by failure to return goods described on the face of the packing list within five days of their delivery. 2. delivery (a) delivery will be made free carrier (incoterms), seller's warehouse, science - based industrial park, taiwan (if seller is ite taiwan or ite california) or santa clara, california (if seller is ite california). (b) title to the goods and the entire risk will pass to buyer up on delivery to carrier. (c) shipments are subject to availability. seller shall make every reasonable effort to meet the date(s) quoted or acknowledged; and if seller makes such effort, seller will not be liable for any delays. 3. terms of payment (a) terms are as stated on seller's quotation, or if none are stated, net thirty (30) days. accounts past due will incur a monthly charge at the rate of one percent (1%) per month (or, if less, the maximum allowed by applicable law) to cover servicing costs. (b) se ller reserves the right to change credit terms at any time in its sole discretion. 4. limited warranty (a) seller warrants that the goods sold will be free from defects in material and workmanship and comply with seller's applicable published specifications f or a period of ninety (90) days from the date of seller?s delivery. (b) goods or parts which have been subject to abuse (including without limitation repeated or extended exposure to conditions at or near the limits of applicable absolute ratings) misuse, accident, alteration, neglect, or unauthorized repair or improper application are not covered by any warranty. no warranty is made with respect to custom products or goods produced to buyer's specifications (unless specifically stated in a writing signed by seller). (c) no warranty is made with respect to goods used in devices intended for use in applications where failure to perform when properly used can reasonably be expected to result in significant injury (including, without limitation, navigation, av iation or nuclear equipment, or for surgical implant or to support or sustain life) and buyer agrees to indemnify, defend, and hold harmless seller from all claims, damages and liabilities arising out of any such uses. (d) this paragraph 4 is the only warr anty by seller with respect to goods and may not be modified or amended except in writing signed by an authorized officer of seller. (e) buyer acknowledges and agrees that it is not relying on any applications, diagrams or circuits contained in any literat ure, and buyer will test all parts and applications under extended field and laboratory conditions. notwithstanding any cross - reference or any statements of compatibility, functionality, interchangeability, and the like, the goods may differ from similar goods from other vendors in performance, function or operation, and in areas not contained in the written specifications, or as to ranges and conditions outside such specifications; and buyer agrees that there are no warranties and that seller is not respo nsible for such things. (f) except as provided above, seller makes no warranties or conditions, express, implied, or statutory; and seller expressly excludes and disclaims any warranty or condition of merchantability or fitness for particular purpose or ap plication. 5. limitation of liability (a) seller will not be liable for any loss, damage or penalty resulting from causes beyond its reasonable control, including but not limited to delay by others, force majeure, acts of god, or labor conditions. in any suc h event, the date(s) for seller's performance will be deemed extended for a period equal to any delay resulting. (b) the liability of seller arising out of the contract or any goods sold will be limited to refund of the purchase price or replacement of pur chased goods (returned to seller freight pre - paid) or, with seller?s prior written consent, repair. (c) buyer will not return any goods without first obtaining a customer return order number. (d) as a separate limitation, in no event will seller be liable for costs of substitute goods; for any special, consequential, incidental or indirect damages; or loss of use, opportunity, market potential, and/or profit on any theory (contract, tort, from third party claims or otherwise). these limitations shall apply notwithstanding any failure of essential purpose of any remedy. (e) no action against seller, whether for breach, indemnification, contribution or otherwise, shall be commenced more than one year after the cause of action has accrued, or more than one yea r after either the buyer, user or other person knew or with reasonable diligence should have known of the matter or of any claim of dissatisfaction or defect involved; and no such claim may be brought unless seller has first been given commercially reasona ble notice, a full written explanation of all pertinent details, and a good faith opportunity to resolve the matter. (f) buyer expressly agrees to the limitations of this paragraph 5 and to their reasonableness. 6. substitutions and modifications seller may at any time make substitutions for product ordered which do not materially and adversely affect overall performance with the then current specifications in the typical and intended use. seller reserves the right to halt deliveries and shipments and alter specifications and prices without notice. buyer shall verify that the literature and information is current before purchasing. 7. cancellation (a) the contract may not be canceled by buyer except with written consent by seller and buyer's payment of reasonab le cancellation charges (including but not be limited to expenses already incurred for labor and material, overhead, commitments made by seller, and a reasonable profit). (b) in no event will buyer have rights in partially completed goods. 8. indemnification seller will, at its own expense, assist buyer with technical support and information in connection with any claim that any parts as shipped by seller under this purchase order infringe any valid and enforceable copyright, or trademark, provided however, t hat buyer (i) gives immediate written notice to seller, (ii) permits seller to participate and to defend if seller requests to do so, and (iii) gives seller all needed information, assistance and authority. however, seller will not be responsible for infri ngements resulting from anything not entirely manufactured by seller, or from any combination with products, equipment, or materials not furnished by seller. seller will have no liability with respect to intellectual property matters arising out of produc ts made to buyer's specifications, code, or designs. except as expressly stated in this paragraph 8 or in another writing signed by an authorized officer, seller makes no representations and/or warranties with respect to intellectual and/or industrial prop erty and/or with respect to claims of infringement. except as to claims seller agrees in writing to defend, buyer will indemnify, defend and hold harmless seller from all claims, costs, losses, and damages (including attorneys fees) against and/or arising out of goods sold and/or shipped hereunder. 9. no confidential information seller shall have no obligation to hold any information in confidence except as provided in a separate non - disclosure agreement signed by both parties. 10. entire agreement (a) these ter ms and conditions are the entire agreement and the only representations and understandings between seller and buyer, and no addition, deletion or modification shall be binding on seller unless expressly agreed to in a writing signed by an officer of seller . (b) buyer is not relying upon any warranty or representation except for those specifically stated here. 11. applicable law the contract and all performance and disputes arising out of or relating to goods involved will be governed where seller is ite taiwan by the laws of taiwan, republic of china or, where seller is ite california, by the laws of california and the united states of america, in either event without reference to the u.n. convention on contracts for the international sale of goods or to confli ct of laws principles. buyer agrees at its sole expense to comply with all applicable laws in connection with the purchase, use or sale of the goods provided hereunder and to indemnify seller from any failure by buyer to so comply. without limiting the fo regoing, buyer certifies that no technical data or direct products thereof will be made available or re - exported, directly or indirectly, to any country to which such export or access is prohibited or restricted under u.s. law or regulations, unless prior authorization is obtained from the appropriate officials and agencies of the government as required under u.s. laws and regulations. 12. jurisdiction and venue where seller is ite taiwan, the courts located in hsinchu, taiwan, republic of china, will have the sole and exclusive jurisdiction and venue over any dispute arising out of or relating to the contract or any sale of goods hereunder. where seller is ite california, the courts located in santa clara county, california, usa, will have the sole and exclusi ve jurisdiction and venue over any dispute arising out of or relating to the contract or any sale of goods hereunder. buyer hereby consents to the jurisdiction of such courts. 13. attorneys' fees reasonable attorneys' fees and costs will be awarded to the pr evailing party in the event of litigation involving and/or relating to the enforcement or interpretation of the contract and/or any goods sold under it.
www.ite.com.tw www.iteusa.com headquarters: 3f, no. 13, innovation rd.1, science - based industrial park, hsin - chu, taiwan 300, r.o.c. tel: 886 - 3 - 5798658 fax: 886 - 3 - 5794803 asia sales office: 7f, no. 435, nei hu district, jui kua ng road, taipei 114, taiwan, r.o.c. tel: 886 - 2 - 26579896 fax: 886 - 2 - 26578561, 26578576 contact person: p.y. chang e - mail: py.chang@ite.com.tw ite (u.s.a. west) inc.: 1235 midas way, sunnyvale, ca 94086, u.s.a. tel: (408) 5308860 fax: (408) 5308861 conta ct person: david lin e - mail: david.lin@iteusa.com ite (u.s.a. eastern) inc.: 896 summit st., #105, round rock, tx 78664, u.s.a. tel: (512) 3887880 fax: (512) 3883108 contact person: don gardenhire e - mail: don.gardenhire@iteusa.com

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